8bit Multiplier Verilog: Code Github

# 8-bit Multiplier in Verilog
Simple shift-add architecture using full adders and half adders.
yosys -p "read_verilog src/*.v; synth_xilinx -top top_multiplier; write_json multiplier.json"

clk    : Pin E3  (100 MHz onboard clock)
rst_n  : Pin C2  (Button center)
A[7:0] : Pin J15, J14, J13, J12, H15, H14, H13, H12 (Switches)
B[7:0] : Pin K15, K14, K13, K12, L15, L14, L13, L12 (Switches)
P[15:0]: Pin R11, R10, R9, R8, T11, T10, T9, T8, 
          U11, U10, U9, U8, V11, V10, V9, V8 (LEDs)
done   : Pin R12 (LED)

This repository contains an efficient 8-bit multiplier implemented in Verilog HDL. The design performs multiplication of two 8-bit unsigned numbers and produces a 16-bit product. Three different architectures are implemented for comparison: array multiplier, carry-save multiplier, and Wallace tree multiplier.
If you are learning digital design or cannot use the * operator, you can implement the multiplication using the "Shift and Add" algorithm (similar to how we do long-hand multiplication on paper). 8bit multiplier verilog code github
`timescale 1ns / 1ps
module multiplier_8bit_struct(
input [7:0] A,
input [7:0] B,
output reg [15:0] Product
);
integer i;
reg [15:0] temp_a;
reg [15:0] temp_b;
always @(*) begin
    temp_a = 81'b0, A; // Zero extend A to 16 bits
    temp_b = 81'b0, B; // Zero extend B to 16 bits
    Product = 16'd0;
// Shift and Add Algorithm
    for (i = 0; i < 8; i = i + 1) begin
        if (B[i] == 1'b1) begin
            Product = Product + (temp_a << i);
        end
    end
end

endmodule


Booth multiplication reduces the number of partial products by encoding overlapping groups of bits. For an 8-bit multiplier, radix-4 (modified Booth) reduces 8 partial products to 4 or 5. # 8-bit Multiplier in Verilog Simple shift-add architecture
module booth_multiplier_8bit (
    input signed [7:0] a, b,   // signed 8-bit inputs
    output signed [15:0] product
);
    reg signed [15:0] pp [0:3];
    integer i;
always @(*) begin
    // Radix-4 Booth encoding of B
    // Simplified example: actual impl requires recoding logic
    for (i = 0; i < 4; i = i + 1) begin
        case (b[2*i+1], b[2*i], b[2*i-1])
            // ... booth encoding cases
            default: pp[i] = 16'sb0;
        endcase
    end
    product = pp[0] + pp[1] + pp[2] + pp[3];
end

endmodule

Why use Booth?

Hardware cost: Moderate — requires encoder, muxes, and an adder tree. clk : Pin E3 (100 MHz onboard clock)

// half_adder.v
module half_adder(
    input a,
    input b,
    output sum,
    output carry
    );
assign sum = a ^ b;
    assign carry = a & b;
endmodule
// full_adder.v
module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
    );
assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (cin & (a ^ b));
endmodule