The adoption of DFT is driven by ruthless economics. The cost of a test vector set and its application time directly adds to the final price of every chip shipped. A chip that is "untestable" is unsellable. More critically, for safety-critical systems (ISO 26262 in automotive, DO-254 in aerospace), testability is a compliance requirement. Fault coverage—the percentage of detected faults—must exceed 99% for many applications. Only systematic DFT can achieve this.
Philosophically, DFT represents a maturation of engineering. Early computer design was an act of heroic creation; testing was an afterthought. Modern design, however, recognises that complexity breeds opacity. By inserting scan chains and BIST modules, the engineer voluntarily surrenders a small amount of area (typically 5-10%) and a small performance penalty for the immense gain of visibility and control. It is an acknowledgment that a system one cannot inspect is a system one cannot trust.
Original DFF:
always @(posedge clk) q <= d;
Scan flip-flop:
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else if (scan_en) q <= scan_in;
else q <= d;
Scan chain: scan_in → FF0 → FF1 → ... → FFn → scan_out digital systems testing and testable design solution
Test process:
Digital systems are prone to manufacturing defects (shorts, opens, process variations) and design errors. Testing ensures: The adoption of DFT is driven by ruthless economics
Testable design means adding extra circuitry to make internal nodes controllable and observable, drastically reducing test cost and time.
The solution to the "testability crisis" relies on three core pillars: controllability, observability, and repeatability. Scan flip-flop: always @(posedge clk or negedge rst_n)
| Metric | Formula / Meaning | |--------|-------------------| | Fault coverage | Detected faults / Total faults | | Test escape | 1 – fault coverage | | Yield | Good chips / total chips | | Defect level | ( (1 - \textyield)^1 - \textfault coverage ) | | Test cost | (Test time × tester hourly rate) + DFT area overhead |
Target: > 99% stuck-at fault coverage for digital ICs.